EE 5301: VLSI Design Automation I

Course Info

EE5301 - Fall Semester 2006
Course web page: http://www.ece.umn.edu/users/kia/Courses/EE5301
Class mailing list: follow these instructions to subscribe (accept the certificate, choose EE5301. If you choose to receive the daily digest, then you will not receive individual messages as they are posted: instead they will be aggregated into a single message and sent to you at the end of the day).
 WebCT page: http://webct.umn.edu/ (click on myU login, then choose "my Toolkit" in myU, and choose 5301 under "WebCT Vista". You can start directly from myU too: http://www.myU.umn.edu , WebCT Vista. Note to on-campus students: you can watch the class video with a 10day delay (UNITE policy) )
UNITE page:
http://www.unite.umn.edu/streaming-video/index.shtml
Class:
MW 4:40pm - 5:55pm, ME212 (09/06/2006 - 12/13/2006)
Two mid-term Exams:
Monday Oct 16, Wednesday November 29, both open notes, open book, and in class
Final Exam: No final exam. Final project instead. Due Wed Dec 6.

Catalog Description:

Basic graph/numerical algorithms. Algorithms for logic/high-level synthesis. Simulation algorithms at logic/circuit level. Physical-design algorithms.

Textbook

[Sait99] Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation: Theory and Practice", World Scientific Publishing Company; 1st edition (November 15, 1999), ISBN: 9810238835.
(only this book is required)
[Mic94] G. De Micheli, “Synthesis and Optimization of Digital Circuits”, McGraw-Hill, 1994.
[CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest, “Introduction to Algorithms”, MIT Press, 1990.
[Sar96] M. Sarrafzadeh, C. K. Wong, “An Introduction to VLSI Physical Design”, McGraw-Hill, 1996.
[She99] N. Sherwani, “Algorithms For VLSI Physical Design Automation”, Kluwer Academic Publishers, 3rd edition, 1999.

Administrative

Please check the "Announcements" link regularly.

Grading:

Policies:

Personnel:

Instructor Kia Bazargan (call me Kia)
Email: kia@ece.umn.edu
Phone: (612) 625-4588 
Office: EE/CSci 4-159 
Office hours: MW 3:30-4:30pm (or by appointment)
   
TA Pongstorn Maidee
 
Email: ee5301@hotmail.com
Phone: 612-626-7163
Office: 4-162 EE/CSci
Office hours: 2:00 - 3:00 TTh

Course Outline / Approximate Schedule

Week # Lecture topics Book Chapters
1 Introduction
   EDA industry roadmap
   Design methodologies
[Ger99] Ch 1-2
[She99] Ch 1
2-4  (2½ weeks) Algorithms
  Time complexity
  Problem tractability
  Deterministic algorithm classes
  Graph algorithms
    DFS, BFS
    Dijkstra's algorithm
    Minimum spanning tree- Prim
[Ger99] Ch 3-5,
[Sar96] Ch 1,
[CLR90] Ch 23-25
4-6  (2½ weeks) Partitioning
  Kerlighan-Lin
  Fiduccia-Mattheyses
  hMetis
[Ger99] Sec. 7.5
[Sar96] Ch 2
7-9 (2½ weeks) + Midterm Floorplanning
  Slicing floorplan sizing
  Wong-Liu's simulated annealing alg
[Ger99] Ch 8
[Sar96] Ch 2
10-11 (1½ weeks) Placement
  Simulated annealing
  Force-directed
  Partitioning-based
  Recent placement algorithms
 
11-13 Routing
  Global routing
  Steiner-tree
  Maze-routing
  Detailed routing: Channel routing
    Vertical/Horizontal constraint graphs
    Left-edge algorithm
    Greedy channel routing
    FPGA routing
[Ger99] Ch 9
[She99] Ch 8-9
14-15 High-level Synthesis
  Scheduling
[Mic94] Ch 4-5


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