EE 5324: VLSI Design II

Spring 2006

Homework #2: Brent-Kung Adder (100 points)

Layout and simulate a 16-bit Brent-Kung adder. You will submit this assignment in two phases. In the first phase, you submit the layout of your p, g and circle operator units, as well as simulation results that show that these units work. Also, submit a report that explains features of your desing, and how you made sure it works correctly. The report should also contain a rough sketch of the floorplan of your final layout. In the second phase, you will submit the complete adder along with simulation results and characterization (area, delay) of your design.

Part of the grade for this assignment is the way you choose test cases and the way you argue that your design works correctly.

What to submit

When submitting your files electronically, zip all files into one file <yourFirstName_yourLastName>.zip (or .tar.gz). For example, if your name is Terry Gross, your file should be named terry_gross.zip. If you want to submit your "hardcopy" reports electronically, I'd be more than delighted to receive them in .pdf or .doc formats. Include the report in the zip file. These are the items you should submit for each phase:

Grading: