Information Regarding Our Usage of Cadence Tools:
- Verilog is used in the senior-level courses
EE 4301, Digital Design with Programmable Logic, and
EE 4363 / CSci 4203,
Computer Architecture and Machine Organization.
- PSPICE is used in several core undergraduate courses:
EE 2001, Introduction to Electronic and Electrical Circuits,
EE 2011, Linear Systems and Circuits
and EE 3115, Analog and Digital Electronics.
- Circuit design and layout tools are used in the
EE 5323, VLSI Design I and
EE 5324, VLSI Design II.
- Analog and mixed-signal chip design tools are used in the
EE 5333, Analog Integrated Circuit Design and
EE 8337, Analog Circuits for Wire/Wireless Communications, as well as in
Prof. Ramesh Harjani's research group
Prof. Chris Kim's research group.
- Digital design and verification tools are used in
Prof. Gerald Sobelman's research group.
This web page is maintained by
Prof. Gerald E. Sobelman
last updated on July 22, 2019.
Cadence is a registered trademark of Cadence Design Systems, Inc.,
2655 Seely Avenue, San Jose, CA, 95134.