The Final Exam on August 8 will be closed book, closed notes,
no calculators and
no electronic devices. You may bring two 8.5" by 11" information
sheets with anything you want written on both sides.
The exam will
cover all of the material in the Lecture Notes, the material in
in Chapters 2, 3, 4, 5 and 8 of the text and the Verilog code examples
discussed in class.
To access Verilog-XL in the IT workstation lab (room EE/CS 4-250) type:
module load ecad/cadence/LDV
To run Verilog-XL on a list of source files file1.v, file2.v, file3.v, type:
verilog file1.v file2.v file3.v
To access online documentation about Verilog-XL, type:
cdsdoc and select Verilog-XL Turbo and then Verilog-XL User Guide.
The documentation will appear in a browser.