`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:53:33 06/20/2008 
// Design Name: 
// Module Name:    clock_divider1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider1(clkin, clkout);
    input clkin;
    output clkout;
	parameter  timeconst = 55;//38; 
	integer count0=0;
	integer count1=0; 
	integer count2=0;
	integer count3=0;
	reg d;
	initial d = 1'b0;
	initial clkout = 1'b0;
	reg clkout;
	
	always @(posedge clkin)
	begin
		count0 <= count0+1;
		if(count0 == timeconst)
			begin
				count0 <= 0;
				count1 <=count1+1;
			end
		else if(count1 == timeconst)
			begin
				count1 <= 0;
			   count2 <= count2 + 1;
			   end
		else if(count2 == timeconst)
			begin
				count2 <= 0;
				count3 <= count3+1;
			end
		else if(count3 == timeconst)
			begin
				count3 <= 0;
				d <= ~(d);
			end
		clkout <= d;
	end
endmodule