Compiling source file "mult6by4.v"
Compiling source file "tbenew.v"
Highest level modules:
tbenew

num_correct =        1024, num_wrong =           0
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Jan 26, 2007  18:05:45