Compiling source file "tb7xy8z.v"
Compiling source file "xy8z.v"
Compiling source file "mult6by4.v"
Highest level modules:
tb7xy8z

                  10  (36 *  1) +(8 *  9) =  108 ( 108)
                  20  (35 * 13) +(8 * 13) =  559 ( 559)
                  30  (37 *  2) +(8 *  1) =   82 (  82)
                  40  (13 *  6) +(8 * 29) =  310 ( 310)
                  50  (45 * 12) +(8 * 25) =  740 ( 740)
                  60  ( 6 *  5) +(8 * 10) =  110 ( 110)
                  70  (37 *  7) +(8 * 18) =  403 ( 403)
                  80  (15 *  2) +(8 * 14) =  142 ( 142)
                  90  (40 *  5) +(8 * 28) =  424 ( 424)
                 100  (61 * 13) +(8 *  5) =  833 ( 833)
                 110  (35 * 10) +(8 *  0) =  350 ( 350)
                 120  (32 * 10) +(8 * 29) =  552 ( 552)
                 130  (22 *  3) +(8 * 13) =  170 ( 170)
                 140  (19 * 11) +(8 * 21) =  377 ( 377)
                 150  ( 2 * 14) +(8 * 29) =  260 ( 260)
                 160  (15 *  3) +(8 * 10) =  125 ( 125)
                 170  (10 * 12) +(8 * 18) =  264 ( 264)
                 180  (10 *  1) +(8 * 24) =  202 ( 202)
                 190  (56 *  9) +(8 * 11) =  592 ( 592)
                 200  (54 *  6) +(8 * 14) =  436 ( 436)
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Jan 27, 2007  12:43:29