Compiling source file "tbexy8z.v"
Compiling source file "xy8z.v"
Compiling source file "mult6by4.v"
Highest level modules:
tbexy8z

num_correct =       32768, num_wrong =           0
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.3 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Jan 27, 2007  12:49:20