EE 4301 Homework Assignment 2

(a) Modify the Verilog code in the file booth16f.v to create the alternate design in which the repeated MSB terms in the a, b, c and d partial products have been separately summed. (In other words, use the array of terms shown on page 7 of the lecture notes for July 18.)

(b) Use the testbench tb16.v (replacing the original booth multiplier with the new design of part (a)) to perform an exhaustive set of signed multiplications to prove that your code of part (a) is correct.

(a) Create a Verilog module for the 8-bit Kogge-Stone adder shown on page 9 of the Adder Designs lecture notes. The inputs to the module are two 8-bit operands and the carry in to the LSB. The outputs of the module are the 8-bit sum and the carry out of the MSB. To do this, first create a module for the operator "o" and then use multiple instances of this operator as specified in the diagram of the Kogge-Stone architecture. You will also need to include additional logic to form the the bit-level propagate, generate, carry and sum functions.

(b) Create a Verilog testbench for the Kogge-Stone adder of part (a) to perform 50 random unsigned additions and display the results (in decimal), including check values. Be sure to randomly select both 8-bit operands as well as the value of the carry in to the LSB. Note that you will have to concatenate the carry out of the MSB with the 8-bit sum value to form the complete 9-bit unsigned result of the addition operation.

(c) Create a Verilog testbench for the Kogge-Stone adder of part (a) to perform an exhausive set of unsigned additions, including all possible combinations of 8-bit operands and carry in values. Use this testbench to prove that your design of part (a) is correct.