EE 4301: Digital Design with Programmable Logic - Summer 2008
MWF 8:00 - 9:55 AM, Room ME 212
Lab: TuTh 12:20 - 2:15 PM, Room EE/CS 1-202
Course Details
Instructor: Gerald E. Sobelman, 612-625-8041, sobelman@umn.edu
Instructor's Office Hours: MWF 3:30 - 4:30 PM, EE/CS 4-157
Text: Advanced Digital Logic Design Using
Verilog, State Machines and Synthesis for FPGAs,,
Sunggu Lee, Thomson, 2006.
Course Web Page:
http://mountains.ece.umn.edu/~sobelman/courses/ee4301/
Midterm Exam: Friday, July 11
Final Exam: Friday, August 8
Grading: Homework 20%, Labs 20%, Midterm Exam 20%,
Final Exam 40%
General Information
Include your student ID number on all homework assignments and exams.
Late homework will not be accepted!
Make-up exams will only be
given for a verified illness or family emergency. If you must miss
an exam,
then the instructor must be notified prior to the start of the exam.
Cheating of any kind is extremely serious and may result in a course grade
of F and/or other consequences.
Outline of Topics Covered
- Introduction to Verilog
-
modeling combinational and sequential logic; test benches; functions
and tasks; behavioral modeling techniques.
- Logic Synthesis with Verilog
-
combinational logic synthesis; sequential logic synthesis.
- Design of State Machines
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state transition diagrams; algorithmic state machine charts; design examples.
- Design of Arithmetic Units
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adders; multipliers; pipelined implementations.
- Floating-Point Arithmetic
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representations; floating-point arithmetic operations.
- Testing Strategies and Design for Testability
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testing combinational logic; testing sequential logic; scan design;
boundary scan; built-in self-test.