General Information
- Syllabus
- Office Hours
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Verilog Examples
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ripple.v
tb1.v
tb3.v
tb5.v
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mult3.v
tb7.v
tbe.v
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mult4bw.v
tb9bw.v
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booth16f.v
tb16.v
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VeSPA Code and Tools
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Reading in L&S: Chapters 2, 3, 4, 6, 7 and Appendix A.
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Reading in P&H: Chapters 1, 2, 3, 5, 6, 7 and Appendix A.
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Class will not meet on March 19, 21 and 23. Instead, the lectures
for those days have been posted at:
WebVista
Homework Assignments
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Homework assignment 1 and solutions have been posted at:
WebVista
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Homework assignment 2 and solutions have been posted at:
WebVista
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Homework assignment 3 and solutions have been posted at:
WebVista
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Homework assignment 4 and solutions have been posted at:
WebVista
Project
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The project information has been posted at:
WebVista
Exams
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The Midterm Exam and solutions have been posted at:
WebVista
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The Final Exam will be given in room Physics 133.
It will be closed book, closed notes, no calculators,
no electronic devices.
You may bring two 8.5" x 11" sheets of paper with anything you want
written on both sides of each sheet.
(Note that any required information about the instruction
fields for VeSPA or MIPS will be provided
to you as part of the exam question.)
The exam covers all of the material in the course.
Verilog Information
- Verilog-XL can be accessed from the CSE computer lab (room 4-250).
Use ssh in Putty to log into one of the following machines:
five.cselabs.umn.edu
four.cselabs.umn.edu
one.cselabs.umn.edu
three.cselabs.umn.edu
two.cselabs.umn.edu
zeus.cselabs.umn.edu
After logging in, type:
module load ecad/cadence/LDV
- To run Verilog-XL on a list of source files file1.v, file2.v, file3.v, type:
verilog file1.v file2.v file3.v
- To access VCS in the CSE computer lab (room 4-250) type:
module load ecad/vcs
- To compile a list of
source files file1.v, file2.v with VCS, type:
vcs file1.v file2.v
- After compiling with VCS, the simulation is run by typing:
./simv