Project Description
(Turn in a paper copy of your solutions and also email
the Verilog code of all of your designs and testbenches
to: rokh0001@umn.edu)
The Final Exam will be on Saturday, May 10, 10:30 AM - 12:30 PM,
in room EE/CSci 3-210.
The Final Exam will be closed book, closed notes, no calculators,
no electronic devices.
(Any required bit values of the instruction fields
for VeSPA or MIPS will be provided.)
It will cover the following material:
L&S: Chapters 2, 3, 4, 6, 7 and Appendix A.
Verilog coding techniques and examples
discussed in class.
P&H: Sections 3.1, 3.2, 3.3, 3.4 and 3.6 of Chapter 3,
Sections 4.1, 4.2, 4.3 and 4.5 of Chapter 4,
Sections 6.6 and 6.9 (up to and including the subsection "Loop
Unrolling for Multiple-Issue Pipelines") of Chapter 6,
Chapter 7,
Sections 8.1 and 8.2 of Chapter 8 and
Sections 9.3 (up to and including the subsection
"Multiprocessor Cache Coherence"), 9.6 and 9.7 of Chapter 9.
To access Verilog in the IT workstation lab (room EE/CS 4-250) type:
module load ecad/cadence/LDV
To run Verilog on a list of source files file1.v, file2.v, file3.v, type:
verilog file1.v file2.v file3.v
To access the online documentation, type:
cdsdoc and select Verilog-XL Turbo and then Verilog-XL User Guide.
The documentation will appear in a Netscape browser.
A Verilog self-study course is on the Patterson and Hennessy CD.