Compiling source file "mult5by4.v"
Compiling source file "tb7new.v"
Highest level modules:
tb7new

                  10   4 *  1 =   4 (  4)
                  20   9 *  3 =  27 ( 27)
                  30  13 * 13 = 169 (169)
                  40   5 *  2 =  10 ( 10)
                  50   1 * 13 =  13 ( 13)
                  60  22 * 13 = 286 (286)
                  70  13 * 12 = 156 (156)
                  80  25 *  6 = 150 (150)
                  90   5 * 10 =  50 ( 50)
                 100   5 *  7 =  35 ( 35)
                 110  18 * 15 = 270 (270)
                 120  18 * 14 = 252 (252)
                 130   8 *  5 =  40 ( 40)
                 140  28 * 13 = 364 (364)
                 150  13 *  5 =  65 ( 65)
                 160   3 * 10 =  30 ( 30)
                 170   0 *  0 =   0 (  0)
                 180  10 * 13 = 130 (130)
                 190  22 *  3 =  66 ( 66)
                 200  13 *  3 =  39 ( 39)
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.2 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Feb  5, 2008  21:28:27