Compiling source file "mult5by4.v"
Compiling source file "xy4z.v"
Compiling source file "tb7xy4z.v"
Highest level modules:
tb7xy4z

                  10  ( 4 *  1) +(4 *  9) =   40 (  40)
                  20  ( 3 * 13) +(4 * 13) =   91 (  91)
                  30  ( 5 *  2) +(4 *  1) =   14 (  14)
                  40  (13 *  6) +(4 * 61) =  322 ( 322)
                  50  (13 * 12) +(4 * 57) =  384 ( 384)
                  60  ( 6 *  5) +(4 * 42) =  198 ( 198)
                  70  ( 5 *  7) +(4 * 18) =  107 ( 107)
                  80  (15 *  2) +(4 * 14) =   86 (  86)
                  90  ( 8 *  5) +(4 * 28) =  152 ( 152)
                 100  (29 * 13) +(4 * 37) =  525 ( 525)
                 110  ( 3 * 10) +(4 *  0) =   30 (  30)
                 120  ( 0 * 10) +(4 * 29) =  116 ( 116)
                 130  (22 *  3) +(4 * 13) =  118 ( 118)
                 140  (19 * 11) +(4 * 21) =  293 ( 293)
                 150  ( 2 * 14) +(4 * 29) =  144 ( 144)
                 160  (15 *  3) +(4 * 10) =   85 (  85)
                 170  (10 * 12) +(4 * 50) =  320 ( 320)
                 180  (10 *  1) +(4 * 24) =  106 ( 106)
                 190  (24 *  9) +(4 * 43) =  388 ( 388)
                 200  (22 *  6) +(4 * 46) =  316 ( 316)
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Feb  5, 2008  21:53:43