Compiling source file "mult5by4.v"
Compiling source file "xy4z.v"
Compiling source file "tbexy4z.v"
Highest level modules:
tbexy4z

num_correct =       32768, num_wrong =           0
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.5 secs in simulation
End of Tool:    VERILOG-XL      04.10.005-s   Feb  5, 2008  21:55:59