EE 4363 /CSci 4203 - Computer Architecture and Machine Organization
Spring Semester, 2008
Homework Assignment 1
Due: Friday, February 8
-
(a) Draw the diagram for a 5-bit by 4-bit
unsigned multiplier
using the same style as for the 3-bit by 3-bit design discussed in
class.
(b) Modify the Verilog code of the example
mult3.v to create a
structural model for this circuit.
(c) Modify the
tb7.v and
tbe.v
testbenches to
perform 20 random multiplications and an exhaustive set
of multiplications, respectively, to demonstrate that your
code is correct.
-
(a) Consider the design of a functional block to compute (X*Y) + (4*Z),
where X is a 5-bit unsigned number,
Y is a 4-bit unsigned number and
Z is a 6-bit unsigned number. What is the decimal
value of the largest result that could be produced? What is the
least number of bits required to represent this value?
(b) Use the 5-bit by 4-bit unsigned multiplier design of the previous problem
together with an optimized ripple carry adder
to create this functional block.
(The ripple carry adder should
contain a minimum number of
half adders and full adders, using full adders only where
they are necessary.)
Draw a diagram which clearly shows how the individual components
are connected together to form the complete design.
(c) Create the
structural Verilog code for this circuit.
(d) Create
testbenches to perform
perform 20 random (X*Y) + (4*Z) calculations and an exhaustive set
of (X*Y) + (4*Z) calculations to demonstrate that your
circuit and code are correct.