EE 4363 /CSci 4203 - Computer Architecture and Machine Organization
Spring Semester, 2008

Homework Assignment 2
Due: Monday, March 31

  1. Consider the following portion of a VeSPA assembly language program: 
    add	r14, r15, r16	;	instruction 1
sub	r16, r17, r15	;	instruction 2
or	r14, r16, r17	;	instruction 3
    1. Identify any flow dependences, anti-dependences and output dependences that exist amongst these instructions. (In each case, specify the register that is involved.)


    2. Suppose that instruction 1 is in the instruction fetch (IF) stage of the 5-stage pipelined VeSPA implementation during cycle 21. Determine which cycles instructions 1, 2 and 3 will be in the write back (WB) stage of the pipeline. (Include a table that shows the instructions moving through the pipeline as part of your answer.)


  2. Here is a series of address references given as word addresses: 2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, 11. Show the hits and misses and the final cache contents for a direct-mapped cache with one-word blocks and a total size of 16 words.


  3. Here is a series of address references given as word addresses: 5, 10, 2, 12, 5, 18, 2, 5, 10, 7, 26, 20, 12, 28. Show the hits and misses and the final cache contents for a 2-way set-associative cache with one-word blocks and a total size of 16 words. Assume that LRU replacement is used.


  4. Consider the following parameter values: memory is byte-addressable, the virtual address is 40 bits, the page size is 32K bytes and each page table entry is 32 bits. Determine the number of bits in the virtual page number field, the number of bits in the page offset field, the number of page table entries and the total size (in Mbytes) of the page table.