In this project you will design the Verilog code for a pipelined implementation of an 8-point Fast Fourier Transform (FFT) processor based on the decimation-in-time (DIT) signal flow graph. You will use 10-bit fixed-point signed arithmetic operators with truncation and scaling, including complex adders, subtractors and multipliers. You will verify each of the components and the complete FFT design using self-checking testbenches.

Design the processor by carefully following the sequence of steps given below. Make sure that your code contains a large number of comments so that it will be clear to the grader how your design has been constructed. Turn in your Verilog code of the designs and the testbenches created in each step, as well as the output produced by the testbenches.

VERY IMPORTANT: Each student must work independently. Do not copy someone else's code!

1. (a) Design a ripple-carry adder module for adding two 10-bit signed numbers by first sign-extending each operand to 11 bits, adding the sign-extended values and then returning the 10 most significant bits (MSBs) of the sum as the output of the module. Note that you must correctly scale the power-of-two weights of these output bits when interpreting the numerical value that is produced at the output. Also, note that the truncation may introduce a small error compared to the full-precision result.
   
   (b) Construct a testbench to perform exhaustive testing of this module to prove that your code of part (a) is correct. Note that the check value calculated in your testbench should correctly model the truncation and scaling process used in the design of part (a).



2. (a) Design a ripple-carry subtractor module for subtracting one 10-bit signed number from another by first sign-extending each operand to 11 bits, subtracting the sign-extended values and then returning the 10 MSBs of the difference as the output of the module. Note that you must correctly scale the power-of-two weights of the output bits. Also, note that the truncation may introduce a small error compared to the full-precision result.
   
   (b) Construct a testbench to perform exhaustive testing of this module to prove that your code of part (a) is correct. Note that the check value calculated in your testbench should correctly model the truncation and scaling process used in the design of part (a).



3. (a) Extend the designs of the adder and subtractor above to construct a complex adder and a complex subtractor, respectively. In other words, the complex adder will use two instances of the above adder, one for the real part and one for the imaginary part, and similarly for the complex subtractor.
   
   (b) Construct a testbench to perform 50 random, truncated, scaled complex additions and 50 random, truncated, scaled complex subtractions. Include the calculation of appropriate check values.



4. (a) Modify the Verilog code in the file booth16f.v to obtain the corresponding code for a 10-bit by 10-bit Booth-encoded signed multiplier. Further modify the design by truncating the product so that only the 10 MSBs of the product are output from the module. Note that you must correctly scale the power-of-two weights of the output bits. Also, note that the truncation may introduce a small error compared to the full-precision result.
   
   (b) Modify the tb16.v testbench to perform an exhaustive set of 10-bit by 10-bit signed, truncated, scaled multiplications to prove that your code of part (a) is correct. Assume that one of the operands is an integer in the range [-512, 511] and the other operand is a fraction in the range [-1, 511/512]. Include the calculation of appropriate check values which correctly model the truncation and scaling process used in the design of part (a).



5. (a) Construct a complex multiplier by using four instances of the multiplier design of the previous step, together with one instance of the complex adder and one instance of the complex subtractor.
   
   (b) Construct a testbench to perform 50 random, truncated, scaled complex multiplications. Include the calculation of appropriate check values which correctly model the truncation and scaling process that is used.



6. (a) Construct 4 modules for DIT butterfly operators, as shown in Figure 1, corresponding to 4 possible values of the twiddle factors, namely W⁰, W¹, W² and W³. For the butterflies using W⁰ or W², no multiplier module is to be used. (In the case of W², the "multiplication" is implemented by manipulating the real and imaginary parts of the other operand.)
   
   (b) Construct a testbench to perform 50 random, complex-valued tests of the above 4 butterfly modules. Include the calculation of appropriate check values which correctly model the truncation and scaling process that is used.



7. (a) Construct the design for an unpipelined implementation of the complete radix-2, DIT 8-point FFT using the signal flow graph of Figure 2, using instances of the butterfly modules of the previous step.
   
   (b) Construct a testbench to perform 3 FFTs using random complex values for the inputs {r[0], ... , r[7]}. The check values should be computed using quantities of type real and the equation for the Discrete Fourier Transform, which is mathematically equivalent to the FFT. Comment on the accuracy of the results produced by your circuit by comparing them against the check values.



8. (a) Construct the design for a pipelined implementation of the complete radix-2, DIT 8-point FFT by inserting pipeline registers between the first and second stages and between the second and third stages of the design of the previous problem. In other words, pipeline registers should be placed at the locations of the two dashed lines. Each pipeline register should be constructed as a parallel set of D-type flip-flops. (It is not necessary to include a reset capability.)
   
   (b) Construct a testbench, including a clock signal, to perform 3 FFTs using random complex values for the inputs. Compute check values using the method described in the previous step.