EE 4363 / CSci 4203 - Computer Architecture and Machine Organization
Spring Semester 2008,
MWF 12:20 - 1:10 PM, Room ME 108
Instructor: Gerald E. Sobelman, (612) 625-8041, sobelman@umn.edu
Instructor's Office Hours: MWF 2:30-3:20 PM, EE/CS 4-157
TA 1: Fakhrul Rokhani, Tu 4:30-6:00 PM, EE/CS 2-127, rokh0001@umn.edu
TA 2: Sangmin Kim, Th 10:00-11:30 AM, EE/CS 4-147A, sangmin@ece.umn.edu
Text 1: Computer Organization and Design, Revised Printing 3rd Edition,
David A. Patterson and John L. Hennessy,
Morgan Kaufmann, 2007
Text 2: Designing Digital Computer Systems With Verilog,
David J. Lilja and Sachin S. Sapatnekar,
Cambridge University Press, 2004
Course Web Page:
http://mountains.ece.umn.edu/~sobelman/courses/ee4363/
Midterm Exam 1: Friday, February 29
Midterm Exam 2: Friday, April 4
Final Exam (New Date/Time/Location):
Saturday, May 10, 10:30 AM - 12:30 PM, room EE/CSci 3-210
Software: Cadence Verilog-XL and processor-specific tools
Grading: Homework 15%, Project 15%, Midterm Exam 1 20%,
Midterm Exam 2 20%, Final Exam 30%
Notes:
Late homework will not be accepted!
Include your student ID number on all homework assignments and exams.
Make-up exams will only be
given for a verified illness or family emergency. If you must miss
an exam,
then the instructor must be notified prior to the start of the exam.
A grade of incomplete is only given when a small part of the course work
cannot be finished due to a verified illness or family emergency.
Cheating of any kind is extremely serious and may result in a course grade
of F and/or other consequences.
Course Outline
1. Instruction Sets:
Operands and operations,
instruction set architectures, assembly language programming,
Verilog modeling.
2. Computer Arithmetic:
Fixed-point arithmetic, implementations of adders, subtractors,
and multipliers, floating-point arithmetic.
3. Computer Performance Analysis:
Performance factors, metrics and benchmarks.
4. Processor Design Concepts:
Pipelining, pipeline hazards, implementation of pipelined
processors, instruction-level parallelism.
5. Memory System Design:
Memory hierarchy, cache memory,
virtual memory.
6. Computer System Design:
Storage systems, input/output systems,
buses, networks, multiprocessors.