module tb1; // specific input sequence, binary output format

reg  [3:0] a, b;
reg  c;
wire [4:0] s;

// instantiate the 4-bit ripple-carry adder
RCA rca1(a, b, c, s);

// apply a specific set of input vectors every 10 time units
initial begin
    a = 4'b0010; b = 4'b1010; c = 1'b0;
#10 a = 4'b1111; b = 4'b0000; c = 1'b0;
#10 a = 4'b0001; b = 4'b0001; c = 1'b1;
end

// print the input and output values after they change
initial
$monitor($time, "  a = %b", a, " b = %b", b, " c = %b", c, " s = %b", s);

endmodule