Note: The symbol ' stands for Boolean complement.

1. Using only one level of logic, draw the static CMOS circuit for the function:
   z = [(AB + C)DEF]'
   Draw your circuit in such a way that the number of transistor drains at the output node is minimized.



2. Using only one level of logic, draw the static CMOS circuit for the function:
   t = [A(BC + DEF)]'
   Draw your circuit in such a way that the number of transistor drains at the output node is minimized.



3. Using only one level of logic, draw the static CMOS circuit for the function:
   f = [(A + B)(C + D) + E]'
   Draw your circuit in such a way that the number of transistor drains at the output node is minimized.



4. Using only one level of logic, draw the static CMOS circuit for the function:
   g = [A(B + C) + DE + F]'
   Draw your circuit in such a way that the number of transistor drains at the output node is minimized.



5. Draw a circuit for a 2-input XNOR function using only 3 static CMOS inverters and 2 CMOS transmission gates. (The XNOR function is 1 if both inputs have the same value, and it is 0 if the two inputs have different values.) Make sure that the path from either input to the output passes through at least one inverter. You may use the symbol for an inverter, but do not use the shorthand symbol for a CMOS transmission gate - instead, show its NMOS and PMOS transistors explicitly.



6. A circuit consists of three MOS transistors with their drains tied together. The common drain node is the function output, f. Possible inputs to each source node are members of the set {0, 1, A, A'}. Possible input to each gate node are members of the set {0, 1, B, B'}. Using these constraints, draw the circuit that implements the function f = AB in such a way that there are no degraded voltage levels at the f output for any combination of values of the A and B inputs. As part of your answer, include a table showing which of the 3 transistors are ON for each input combination and explain why the output voltage level is not degraded in each case.



7. Draw a circuit for a 16-input AND function using two levels of static CMOS logic. Make sure that none of the logic gates in your circuit has more than 4 transistors in series. You may use logic gate macro symbols as part of your answer, but be sure to define the transistor-level structure within each such macro.



8. The following sequence of input pairs (A, B) are applied to the circuit of Figure 1: (0, 0), (1, 0), (1, 1), (0, 1), (1, 1), (0, 1), (0, 0), (0, 1). Give the corresponding sequence of output values, Z, that will be produced by this circuit. (Assume that the input pairs are applied at a slow enough rate that the circuit has enough time to settle to its new output value before the next pair of inputs are applied.)



9. Suppose that the sequence of input pairs given in the previous problem are applied to the circuit of Figure 2. Give the corresponding sequence of output values, Z, that will be produced by this circuit. (Assume that the input pairs are applied at a slow enough rate that the circuit has enough time to settle to its new output value before the next pair of inputs are applied.)
   
   
10. For the circuit of Figure 3, create a table that shows the logic value at the output f and whether transistors N1, N2 and P1 are ON or OFF for each of the 4 possible input combinations. Is the output voltage level degraded for any of the input combinations? Explain.