EE 5323 Homework Assignment 2

Consider the circuit of Problem 1 of Homework Assignment 1. Specify the relative widths of the transistors so that (under worst-case conditions) the ON-resistances of the pull-up net and the pull-down net are the same as those for the reference inverter, assuming that gamma = mu = 3. Also, compute the logical effort for each of the 6 inputs.

Consider the circuit of Problem 3 of Homework Assignment 1. Specify the relative widths of the transistors so that (under worst-case conditions) the ON-resistances of the pull-up net and the pull-down net are the same as those for the reference inverter, assuming that gamma = mu = 2. Also, compute the logical effort for each of the 5 inputs.

Consider the logic diagram of Figure 1. In the figure, the capacitance C has the value 24 fF, where 1 fF = 10^-15 F. The transistor gate capacitance per unit width is 2 fF/micron. Find the set of transistor widths in the three logic gates along the path from A to B that minimizes the delay along this path, assuming that gamma = mu = 2. Be sure to specify the transistor widths in microns.

The state transition diagram for a finite state machine (FSM) is shown in Figure 2. There is one input, X, one output, Y, and one state variable, A. The transitions are labeled as X/Y and the states are labeled according to the value of A. Use two-phase clocking (i.e., where phase 2 is the complement of phase 1) and assume that the input signals are latched on phase 1. Draw the transistor-level circuit diagram for this FSM using a static CMOS PLA to generate the next-state and output functions. Use the drawing style for the PLA that was discussed in class. Include static D-type latches for the input, output and state signals. (Use a design that includes a transmission gate and a weak feedback inverter.) Also, include extra delay in the feedback path to prevent a hold-time violation. You may use macro symbols, but be sure to completely specify the transistor-level circuitry within each such symbol. You do not have to specify the widths of the transistors in this circuit.

Using only one level of logic, draw the static CMOS circuit for the following function (where ' indicates the Boolean complement):

g = [f(A, B, C, D, E)]'

where f is the majority function of 5 variables. In other words, f = 1 if a majority of the 5 inputs are 1 and f = 0 otherwise. [Hint: The function is self-dual.] Draw your circuit in such a way that the number of transistor drains at the output node is minimized. You do not have to specify the widths of the transistors in this circuit.