EE 5323 - VLSI Design I
Fall Semester, 2002

Homework Assignment 3
Due: Wednesday, November 6

  1. A finite state machine (FSM) has two inputs, X and Y, one output, Z, and two state variables, A and B. The next-state and output equations for this FSM are as follows:

    Anext = X'A + Y'B , Bnext = XA' + YB , Z = XA' + YB'

    (' indicates Boolean complement.) Use two-phase clocking (i.e., where phase 2 is the complement of phase 1) and assume that the input signals are latched on phase 1. Draw the transistor-level circuit diagram for this FSM using a domino CMOS PLA (without any evaluate transistors in the OR-plane) to generate the next-state and output functions. Use the drawing style for the PLA that was discussed in class. Include dynamic D-type latches (i.e., built using a transmission gate and an inverter) for the input, output and state signals. You may use macro symbols, but be sure to completely specify the transistor-level circuitry within each such symbol. You do not have to specify the widths of the transistors in this circuit.


  2. A proposed edge-triggered D-type flip-flop is shown in Figure 1. (The weak inverter has a weak PMOS and a weak NMOS.)

    (a) Is this a rising-edge triggered or falling-edge triggered flip-flop?

    (b) Is Z the true or the complement Q output?

    (c) For the 4 possible combinations (current value of Z, next D to be stored), state what will happen at node X and node Y during the evaluate phase.

    (d) Dynamic power dissipation is due to the charging and discharging of capacitive nodes. Based on your answer to part (c), briefly explain why this circuit might be useful for low-power applications.


  3. Consider the function f = BC + XOR(A, C), where XOR is the exclusive-OR function. Assume that true and complement forms of A, B and C are available as inputs.

    (a) Write the nested if-then-else logic statements corresponding to this function and its complement. Let A be the outer (i.e., the first) binary decision block, B be the middle binary decision block and C be the inner binary decision block. Indicate which, if any, of these binary decision blocks may be shared or eliminated, and give the minimum number of A-blocks, B-blocks and C-blocks that are required.

    (b) Draw the dynamic DCVS (i.e., dual-rail domino) circuit corresponding to the if-then-else description of part (a), using the minimum number of NMOS transistors in the merged pull-down network. Be sure that your circuit is robust against charge sharing and noise. You do not have to specify transistor widths.


  4. In this problem, you will perform circuit simulations for the circuit of Figure 2. The dynamic DCVS full adder is the design discussed in class, the NOR gates are static CMOS NOR gates, the C-element is the circuit in Figure 1 of Homework 1 and the inverters are static CMOS inverters.

    Assume that the true and complement forms of the input signals x1, x2 and x3 can switch to new values at the midpoint of each precharge phase, and let the values for x1, x2 and x3 during 8 successive clock cycles be as follows: (0, 0, 0), (0, 0, 1), (0, 1, 0), (0, 1, 1), (1, 0, 0), (1, 0, 1), (1, 1, 0), (1, 1, 1). (The complement forms of the inputs have values opposite to these.) Use a 50% duty cycle clock with a clock period that is long enough to allow the output f3 to be computed during the evaluate phase.

    Use the BSIM 3 models (Star-HSPICE level 49) that are available from the MOSIS web site. The fabrication technology is a 0.5 micron CMOS process called HP AMOS14TB, and you will find NMOS and PMOS device model parameters for several fabrication runs at the following web page: http://www.mosis.org/Technical/Testdata/hp-amos14tb-prm.html. The most recent fabrication run is listed first, and the others are listed in reverse-chronological order. Select the parameters from any of the 10 most recent runs. (Note: Occasionally, the parameters in these files give strange results. If you find this to be the case, then use the parameters from another file.) Within any of these files, cut and paste the lines starting with ".MODEL CMOSN NMOS (" so that you will have the NMOS and PMOS device models for that fabrication run.

    Specify L = 0.6U for all NMOS and PMOS transistors. (Note: The transistor model parameter XL will subtract 0.1 micron from this value so that the actual channel length used for the simulations will be the design rule minimum value of 0.5 micron.) For simplicity, use the following width, area and perimeter values: For all NMOS transistors in this circuit, use W = 10.8U, AS = AD = 19.44P, PS = PD = 14.4U. For all PMOS transistors in this circuit (except for keepers), use W = 43.2U, AS = AD = 77.76P, PS = PD = 46.8U. For all PMOS keepers in this circuit, use W = 0.9U, AS = AD = 1.62P, PS = PD = 4.5U. Simulate your circuit under nominal conditions, i.e. with a VDD of 3.3 volts and at the default simulation temperature. VERY IMPORTANT: Hand-annotate your simulation results by tracing over key waveforms with colored pens and adding comments explaining what the waveforms mean. In particular, show that you obtain the correct results for the sum, carry out, f1, f2 and f3 functions during the 8 consecutive clock cycles.