EE 5323 - VLSI Design I
Fall Semester, 2002

Homework Assignment 4
Due: Wednesday, December 11

  1. (10 points) Draw the transistor-level circuit diagram corresponding to the symbolic layout shown in Figure 1. Be sure that the assignment of inputs to specific transistors in series chains corresponds exactly to the layout.


  2. A CPL logic diagram is shown in Figure 2. In your answers to parts (a) and (b), you may use our standard symbol for a static CMOS inverter. Otherwise, show all NMOS and PMOS transistors explicitly.

    1. (15 points) Draw the complete transistor-level circuit corresponding to Figure 2 using standard CPL circuits (i.e., do not use dynamic CPL circuits). Explain why each of the REGEN sub-circuits are needed in this case.


    2. (15 points) Draw the complete, optimized transistor-level circuit corresponding to Figure 2 using dynamic CPL circuits. Be sure to include the auxiliary circuits that produce the rising or falling forms of the input signals, as needed. (Note that you may also have to introduce buffers at internal nodes in order to create the proper signal type.) Be sure to eliminate any unnecessary transistors from the logic gates. What function does each of the REGEN sub-circuits perform in this case?


  3. (30 points) Create the layout for the circuit in Problem 4 of Homework Assignment 3. (Information on using the Magic layout editor is available on the class web page.) Use the 0.5 micron, 3-layer metal, n-well CMOS design rules called SCN3M_SUBM, with lambda = 0.3 micron. (Note that a 0.1 micron shrink is applied to the poly mask prior to fabrication so that the actual minimum channel length will be (2)(0.3) - 0.1 = 0.5 micron.) Information about these design rules is available at: http://www.mosis.org/Technical/Designrules/scmos/.

    You may use the standard cell or gate matrix layout style, or a combination of the two. Be sure to include an adequate number of well and substrate contacts (one contact for every group of 5-10 NMOS or PMOS transistors). Your layout must be completely free of design rule violations. Turn in the following individual layout diagrams: inverter, 2-input NOR gate, C-element, dynamic DCVS full adder, entire circuit.

  4. (30 points) Using the circuit extraction feature of the layout editor, extract the netlist from the layout of the previous problem and perform an HSPICE simulation. (Turn in the first two pages of your extracted netlist, not the whole listing.) Use the same operands, device models, supply voltage and temperature as in Problem 4 of Homework Assignment 3. (You may have to use a different clock period.) Use colored pens to trace over key simulation waveforms and clearly show that you obtain the correct results for the sum, carry out, f1, f2 and f3 functions during the 8 consecutive clock cycles.