EE 5323 - VLSI Design I
Fall Semester, 2002

Homework Assignment 1 Solutions

  1. See Figure 1.


  2. See Figure 2.


  3. See Figure 3.


  4. See Figure 4.


  5. The truth table for the XNOR function is as follows:

    ABf
    001
    010
    100
    111


    Therefore: f = A' if B = 0; f = A if B = 1. One possible implementation of this is shown in Figure 5. (Other correct solutions are also acceptable.)


  6. See Figure 6.


  7. Let:
    r = x1 x2 x3 x4,
    s = x5 x6 x7 x8,
    t = x9 x10 x11 x12,
    u = x13 x14 x15 x16.

    Then the 16-input AND function can be written as: f = (r s t u)'' = (r' + s' + t' + u')'. This leads to to the circuit diagram of Figure 7a, where the NAND and NOR gates are defined in Figure 7b and Figure 7c, respectively.


  8. The corresponding sequence of output values, Z, is as follows: 0, 0, 1, 1, 1, 1, 0, 0. (Note: This circuit is one possible implementation of a C-element or "coincidence element." A C-element has the following behavior: If the two inputs have the same value, then the output becomes that common value. Otherwise, if the inputs have different values, the output retains its previous value.)


  9. The corresponding sequence of output values, Z, is as follows: 0, 0, 1, 1, 1, 1, 0, 0. (Note: This circuit is another implementation of a C-element, so the output sequence is the same as for the previous problem.)


  10. The circuit operation is as follows:

    ABP1N1N2f
    00ONOFFOFF1
    01ONONOFF0
    10OFFOFFON0
    11OFFONON0


    There are no degraded levels for any case because:
    1. When f = 1, P1 is ON.
    2. When f = 0, N1 or N2 (or both) is ON.