EE 5323 - VLSI Design I
Fall Semester, 2002
MWF 3:35 - 4:25 PM, Room EE/CS 3-210

General Information

Instructor: Gerald E. Sobelman, (612) 625-8041, sobelman@ece.umn.edu
Instructor's Office Hours: WF 2:00 - 3:30 PM, EE/CS 4-157
TA1: Kai Chang, kaichang@ece.umn.edu, EE/CS 2-115, (612) 625-3027
TA2: Jaisudh Madhusoodhan, jaisudh@ece.umn.edu, EE/CS 2-115, (612) 625-3027
Text: None
Course Web Page: http://mountains.ece.umn.edu/~sobelman/courses/ee5323/
Midterm Exam 1: Wednesday, October 9 (bring one 8.5" x 11" information sheet)
Midterm Exam 2: Wednesday, November 13 (bring one 8.5" x 11" information sheet)
Final Exam: Thursday, December 19, 1:30 - 3:30 PM (bring one 8.5" x 11" information sheet)
CAD Software: HSPICE and Magic.
Grading System: Homework 20%, Midterm Exam 1 20%, Midterm Exam 2 20%, Final Exam 40%

Notes:
Late homework will not be accepted!

Include your student ID number on all homework assignments and exams.

Make-up exams will only be given for a verified illness or family emergency. If you must miss an exam, then the instructor must be notified prior to the start of the exam.

A grade of incomplete is only given when a small part of the course work cannot be finished due to a verified illness or family emergency.

Cheating of any kind is extremely serious and may result in a course grade of F and/or expulsion from the University.

Course Outline

1. Introduction to CMOS Circuit Design: MOS switch model, design of static CMOS combinational logic functions, transmission gate networks, dynamic and static latches, two-phase clocking, finite-state machines.

2. Performance Optimization of CMOS Circuits: The logical effort model, calculating logical effort of static circuits, transistor sizing for delay minimization, design of asymmetric and skewed logic gates.

3. CMOS Layout Design: CMOS process flows, layout design rules, basic layout techniques, layout of standard cells and larger macros, layout parasitics, modeling of interconnect.

4. Dynamic CMOS Circuit Design: Precharging concept, the cascading problem, domino CMOS, dual-rail domino circuits, clock/latch design for domino circuits, other high-speed circuit techniques.