EE 5327 - VLSI Design Lab - Spring Semester 2008

Format for Final Written Report
Due Date: Tuesday, May 13 before 4:00 PM (turn in to secretary in ECE office)


Each design team will write one report. Use double-spaced pages with 12 point type and organize your report in exactly the following way:

  1. Title Page (1 page)

  2. Project title, design team members, brief abstract of your report.

  3. Design Description (8 to 10 pages)

  4. Describe your design in as much detail as possible. Start with a system block diagram and describe the function of each of the major blocks. Describe the interface between your chip and the external system, and include a table showing each of the pins and their functions. (Do not include any background information about the application area.)

  5. Synthesis Results (pages as needed)

  6. Include any speed/area trade-offs that you considered before settling on your final design, and give the area and delay results for your final implementation. Present the results on fault coverage and scan insertion.

  7. Verification Plan and Simulation Results (pages as needed)

  8. Explain how you went about verifying the correctness of your design, including testbench decisions, simulation of special or unusual cases, formal verification, comparison with Matlab results, etc. You must convince the reader that your design actually works as intended. Use colored pens to highlight important waveforms and add hand-written annotations to explain what the waveforms mean.

  9. Conclusions (3 to 4 pages)

  10. Summarize your report. Explain the difficulties that you faced and how you overcame them. If you were going to create a second-generation version of your chip, what aspects of the design would you change, given what you have learned? What advice would you give to students who will be taking this course in the future?

  11. Appendix A - Verilog Code (pages as needed)

  12. Include the complete Verilog code for your design. Be sure that it contains a large number of carefully written comments so that your code will be clear to the reader. Note: Use single-spaced lines and a Courier font for this section of the report.

  13. Appendix B - Schematics (pages as needed)

  14. Present the synthesized schematic diagrams for your design. Include hand-annotations that explain the function of each major block.
Important: Bear in mind that the writing quality (i.e., spelling, grammar, organization, clarity, neatness, etc.) is important and will be a factor in the assignment of points. Therefore, please take time to proof-read your report carefully!

Design Description
20%
Synthesis Results, Verilog Code, Schematics
30%
Verification Plan, Simulation Results
30%
Conclusions
10%
Writing Quality
10%