EE 5327 - VLSI Design
Lab
- Spring Semester
2008
Project Guidelines
Each design team will consist of two members.
It is
your responsibility to choose a partner. If someone drops out
midway through the course, the other person on the
team must complete the project by him/herself.
So, if you have any doubt about your willingness or ability to complete
the project, please drop the course now.
Do not put someone else in a difficult position!
Each design project must be the original design work of the
team members. While you may make use of generic Verilog programming
structures and techniques such as those discussed in the lectures
and in textbooks,
the main architectural design and Verilog implementation must be the
original design work of the team members. Do not copy or re-use
someone else's Verilog design implementation!
The list of specific design
topics is given below.
Only one
design group will be allowed to have any given topic.
Design topics will be confirmed on a first-come, first-served basis.
As soon as your group is ready,
send an e-mail message to sobelman@umn.edu
giving the two student names, student ID numbers and your first, second and
third choices of project topics.
I will either confirm one of your project choices or else ask you
to select another topic. The project assignment process
must be completed by February 1.
Before selecting a topic, do a literature search on the area(s)
you are interested in to become aware of recent work that has been done.
You should make use of the IEEE Xplore database, which is available
to University of Minnesota students through the library. To access this, go to
www.lib.umn.edu/articles/ej.phtml
and select the link "Collections"
and then the link "IEEE Xplore."
This database contains the full text of
papers published in any IEEE journal or conference since 1988.
To find relevant papers, select the Advanced Search option and use
keyword(s) from
the project topic together with the additional keyword vlsi.
The design project topics
are:
- AES encryption/decryption processor
- Elliptic curve encryption/decryption processor
- Chaotic system encryption/decryption processor
- SHA-1 hash function processor
- MD5 hash function processor
- Adaptive FIR digital filter
- Discrete wavelet transform processor
- Digital filter bank
- Turbo code encoder/decoder
- LDPC encoder/decoder
- Lattice or sphere decoder
- V-BLAST detector
- Decision Feedback Equalizer
- OFDM baseband transceiver (some sub-component(s))
- MIMO baseband transceiver (some sub-component(s))
- MIMO-OFDM baseband transceiver (some sub-component(s))
- OFDM and/or MIMO hardware channel emulator (some sub-component(s))
- JPEG 2000 encoder/decoder (some sub-component(s))
- MPEG-4 encoder/decoder (some sub-component(s))
- H.264 encoder/decoder (some sub-component(s))